1. Field of the Invention
The present invention relates generally to integrated circuit switching power amplifiers, and more specifically, to a circuit and method for protecting against latch-up failures during reset.
2. Background of the Invention
Switching power amplifiers are currently in widespread use in automotive amplifiers and other audio amplifiers. Such amplifiers, sometimes referred to as Class D amplifiers, have higher efficiency than linear amplifiers, making them well suited for battery driven applications and applications where power dissipation in the form of heat is a problem, such as very high power professional audio applications, as in concert halls.
The outputs of switching power amplifiers are typically provided to an inductive load, which typically includes a filter inductor through which the output(s) is series-connected to a filter capacitor that is connected in parallel with the load, which may also be highly inductive, such as a loudspeaker. When the amplifier is reset, the control logic that provides the switching power drive to the output is typically isolated by turning off the drive transistors that switch power to the output terminal(s). However, since the load (including output filtering components) is typically inductive, energy is stored in the inductance of the load and a back-current will occur when the drive transistors are turned off.
When the output driver transistors are integrated on a common substrate, the back-current injects minority carriers through a junction between the output terminal of one of the transistors and the adjoining substrate or well. For example, in a P-type substrate integrated circuit, a current drawn from the output terminal will cause minority carrier injection into the substrate through the drain terminal of the N-channel device that is connected to the output terminal, if the potential of the output is sufficiently below the substrate potential so that the PN junction between the substrate and the drain terminal of the N-channel device turns on. Simultaneously, the substrate may have other PN junctions with N-type diffusions of other devices integrated on the substrate, which effectively form bipolar transistors having a collector at each N-type diffusion on the substrate, the substrate as a base, and the drain terminal of the N-channel output device as an emitter. Therefore, minority carrier injection into the substrate is undesirable in that other devices may be turned on or disrupt the operation of another circuit, for example, changing the state of a stored logical value. In the power output stage, the minority carriers in one device can cause a control change in the complementary device that through feedback turns both parasitic devices on, causing latch-up and failure of the integrated circuit. Alternatively or at the same time, when the injected current is much larger (on the order of 103 or 106) than the nominal current of another high current gain device forming a complementary parasitic transistor with the substrate, then the complementary parasitic transistor can provide an over-current path to cause latch-up and failure of the integrated circuit.
Similarly, a current injected into the output terminal will cause minority carrier injection into the N-well that isolates the drain and source of the P-channel device from the substrate, if the potential of the output terminal is sufficiently above the N-well potential so that the PN junction between the N-well and the drain terminal of the P-channel device turns on. Additionally, the N-well has a PN junction with the substrate, which effectively forms bipolar transistors having collectors at the substrate and each P-type diffusion within the substrate, the N-well as a base, and the drain terminal of the P-channel output device as an emitter. Therefore, minority carrier injection into the N-well is undesirable in that other devices may be turned on, or disrupt the operation of another circuit. In the power output stage, the minority carriers in one device can cause a control change in the complementary device that through feedback turns both parasitic devices on, causing latch-up and failure of the integrated circuit. Alternatively or at the same time, when the injected current is much larger (on the order of 103 or 106) than the nominal current of another high current gain device forming a complementary parasitic transistor with the substrate, then the complementary parasitic transistor can provide an over-current path to cause latch-up and failure of the integrated circuit.
Therefore, when driving an inductive load, techniques such as floating substrates and guard rings as described in: “Substrate Connection in an Integrated Power Circuit”, U.S. Pat. No. 6,737,713, to Georgescu, et al., have been employed to protect against latch-up and disruption or failure of other components such as digital logic that provides control of the switching output stages, which can potentially cause other devices in the integrated circuit to latch-up. However, if there is sufficient energy stored in the inductive load, the protection of the guard rings can be overcome. Even in applications in which power switching transistors are provided external to a switching power amplifier integrated circuit, if the transistors are fabricated as a monolithic element on a common substrate, latch-up can occur in the switching output stage. Further, such guard rings are applicable only in applications in which the power devices are integrated on the same substrate with the guard rings, and therefore will not provide protection for circuits having separate monolithic driver devices, unless the guard rings are integrated in the driver device package itself.
Therefore, it would be desirable to provide a method and apparatus for protecting a switching amplifier integrated circuit from latch-up and power supply disruption due to disabling the output of the amplifier during reset. It would further be desirable to provide an amplifier integrated circuit that is protected during reset for both internally-integrated power switching device applications and when external power switching transistors are employed.